Conventionally, a technology of synthesizing logic circuits by computers is known. As an example of this technology, there is a known behavioral synthesis system that converts behavioral descriptions in which functions of logic circuits are described without being aware of clocks to Register Transfer Level (RTL) descriptions in which functions of registers are described based on the clocks. For example, the behavioral synthesis system performs behavioral synthesis by setting, based on a behavioral description, the scheduling of computation and resource/sharing of computation units and creating data paths and state machines that control the computation contents and the computation timing.
As an example of the behavioral synthesis system, there is a known technology that detects a false path, from among created data paths, in which the entirety of the path does not become active, and that reduces the number of data paths targeted for optimization of the latency. Furthermore, there is a known behavioral synthesis system that considers connections between modules provided in a circuit and that optimizes the positions in which flip-flops (FFs) that adjust the latency are inserted.
Patent Document 1: Japanese Laid-open Patent Publication No. 2001-209670
Patent Document 2: Japanese Laid-open Patent Publication No. 2014-142918
However, with the related technologies, if an automatically created state machine becomes a problem in terms of the operation timing of circuits, because a user rewrites the behavioral description based on the result of the timing analysis obtained by using RTL, there is a problem in that it takes time to design a circuit.
For example, if a user recreates a behavioral description based on the result of the timing analysis, because a behavioral description with a high abstraction level is not able to be described, it is difficult to reduce the Turn Around Time (TAT) of the design or the simulation time. Furthermore, if a user recreates a behavioral description based on the result of the timing analysis, because the user creates the behavioral description by considering the operation timing when a process is actually performed, the behavioral description is not diverted to circuits that have different technologies or operation frequencies and thus the reuse of the behavioral description is decreased. Furthermore, if it is found that a state machine becomes a problem in terms of the operation timing at the time of placement and wiring of a circuit, because a review is performed from a behavioral description, a loss in a process is increased. Consequently, with a method in which a user recreates a behavioral description based on the result of the timing analysis of the RTL, it takes time to design a circuit.
Accordingly, it is an object in one aspect of an embodiment of the invention to provide a state machine dividing program, an information processing apparatus, and a state machine dividing method that reduce the time taken to design a circuit.